(1) Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to chipsets in computer systems.
(2) Background Information
A typical computer system includes a host processor coupled to a chipset (hereinafter referred to as xe2x80x9chost bridgexe2x80x9d). The host bridge may be coupled to an input/output bus such as a Peripheral Component Interconnect (PCI) bus. The host bridge may include a memory controller that is coupled to a system memory. The host bridge serves as an interface between the host processor, the system memory, and the PCI bus.
During a typical read cycle, the processor provides the cycle type and address during the address phase. The address is compared with cache line tags and the result of this comparison is presented on a host bus during the snoop phase. The cache is a high speed memory that contains duplications of most recently used data in the system memory. Many times there is a discrepancy between the cache and the system memory in that the cache has more up-to-date data than the system memory. For any operation that requires access to a cacheable range in the system memory, the host bridge has to check, prior to accessing the actual contents of the system memory, to see if an entry in the cache, that has a tag corresponding to an entry in the system memory, has been modified in any way. If the entry has been modified, the content of the system memory is stale. The respective entry in the cache is extracted and is flushed to the system memory. This whole operation is called xe2x80x9csnoopingxe2x80x9d.
Back-to-back read operations are read operations generated by the CPU at the fastest possible rate. One example of back-to-back reads operation is an operation where the address strobe (ADS#) signal is asserted every three clocks. To process back-to-back read operations to the system memory, the host bridge asserts a request to the system memory for the initial read. After the host bridge asserts a request to the system memory for the initial read, the host bridge waits to sample the result during the snoop phase. If the line in the cache, corresponding to the memory location accessed, is not modified, the host bridge asserts a request to the system memory for a subsequent read. If the line in the cache has been modified, the host bridge first flushes the modified line from the cache to the system memory and then initiates the subsequent read. This creates a critical path from the sampling of the snoop results on the host bus, to the incrementing of a read request pointer that points to the subsequent location in the memory to be read out, to the assertion of the read request to the system memory. At high frequencies, at which current host bridges operate, this critical path, when the line to be read out has been modified in the cache, prevents the assertion of a timely request to the system memory for the subsequent read in the case of back-to-back read operations.
It is desirable to provide a method and an apparatus where fast back-to-back reads are not substantially affected in time by the snoop operation if a line desired to be read out has been modified in the cache.
Briefly an embodiment of the present invention provides a computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.